1. Technical Field
The invention relates generally to output driver circuits and, more specifically, to tri-state output driver circuits with dual-rail differential inputs and self-timed single ended outputs.
2. Background Art
In a tri-state output driver circuit, the output of the circuit should optimally reflect either the inputted data being driven through it (a high logic voltage or a low logic voltage) or be in a tri-state mode, a mode that electrically isolates the output. The accuracy of the data driven through the circuit depends mainly upon the issuance of an Output Enable (OE) signal when the system is ready to receive the data and the presence of the data at the circuit's input devices. The output of the driver circuit should remain in tri-state mode until the data is present at the input (valid) and the OE signal is issued.
Traditionally, the prior art driver circuits are taken out of tri-state mode when the OE signal is issued. Although a system may be ready for the data and will accordingly issue an OE signal, the data may not be present at the input of the driver circuit. Consequently, faulty data may be sent through the circuit. Thus, the OE signal of traditional circuits is delayed for a certain amount of time to ensure the data to be driven is valid.
U.S. Pat. No. 5,159,216, "Precision Tristate Output Driver Circuit Having a Voltage Clamping Feature," (issued October 1992 to Taylor et at. and assigned to TriQuint Semiconductor, Inc.), which is hereby incorporated by reference, discloses a traditional tri-state output circuit in which the OE signal is delayed to ensure the validity of the data. Once the OE signal is issued, the circuit will then drive the inputted data to the output terminal. The data may be present at the input of the driver circuit, but will not be driven through until the OE signal is issued.
This method may be useful in ensuring valid data in slower systems, but can be detrimental in high clock speed systems. The delay of the OE signal becomes a significant portion of overall access time, ultimately degrading the system's performance.
Examples of other driver systems may be found in the following United States Patents and article, which are hereby incorporated by reference: U.S. Pat. No. 5,345,421, "High Speed, Low Noise Semiconductor Storage Device," (issued September 1994 to Iwamura et al. and assigned to Hitachi, Ltd.); U.S. Pat. No. 5,027,326, "Self-timed Sequential Access Multiport Memory," (issued June 1991 to Jones and assigned to Dallas Semiconductor Corporation); and the article "A Low-Power Chipset for a Portable Multimedia I/O Terminal," IEEE Journal of Solid-State Circuits, Vol. 29, No. 12, December 1994, pp. 1415-1428.
Although each aforementioned reference provides a way to operate with various drivers and circuits in a system, they do not disclose a way of improving the access time of a system through a tri-state output driver circuit that will not delay the OE signal without affecting the validity of the data. Accordingly, a need has developed in the art for tri-state driver circuits that are truly self-timed from the arrival of input data.